{"id":673,"date":"2016-02-10T15:17:57","date_gmt":"2016-02-10T15:17:57","guid":{"rendered":"http:\/\/www.pcb4assembly.com\/?p=673"},"modified":"2016-08-25T14:40:31","modified_gmt":"2016-08-25T14:40:31","slug":"helpful-tips-for-applying-dfm-design-for-manufacturing","status":"publish","type":"post","link":"https:\/\/www.eprotos.com\/pcb-blog\/helpful-tips-for-applying-dfm-design-for-manufacturing\/","title":{"rendered":"Helpful tips for applying DFM design for manufacturing"},"content":{"rendered":"

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DFM Design for manufacturing<\/h1>\n
\"PCB4assembly.com\"<\/a>

Eprotos.com<\/p><\/div>\n

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Helpful tips for applying DFM design for manufacturing<\/strong>. When designing High-speed PCB, lack of communication or assumptions between PCB designers and board manufacturers can lead to costly failures. Following are some real-world scenarios in which communication problems have occurred and some tips on how to avoid such problems.<\/p>\n

Stepping through key layout stages –<\/strong><\/p>\n

About 75-80 percent of PCB layout errors occur due to incorrect part geometry or creation, bad hole definition, inadequate spacing between through holes and surface mount components, and lack of rework ability around critical components.<\/p>\n

BGA<\/strong> – As a result the PCB design engineers have to move gingerly through various stages to avoid such fabrication<\/a> and assembly<\/a> problems.\u00a0For example, (BGA) Ball Grid Array’s requiring rework may be placed too close together.\u00a0As a result, rework cannot be performed.\u00a0Also, vias or pads may be too close to the board\u2019s edge, which can cause vias to be cut away during routing. Increased spacing is necessary for BGA efficiency.\u00a0There are other issues arising from BGA use such as coefficient of thermal expansion (CTE) mismatches between the BGA and the boards due to improperly selected PCB material.\u00a0If CTE is not comparable, solder joint fatigue can cause opens on the BGA.\u00a0Also, symmetrical board stack-up is crucial when using BGAs.\u00a0Otherwise, solder joint fatigue and board warping occur.<\/p>\n

Fiducial Marks<\/strong> –\u00a0 There are fiducials, which are marks on a PCB that provide common measurable points for each and every assembly step.\u00a0They permit PCB assembly systems to precisely zero in on the circuit pattern. Fiducials are used to properly align (SMT) surface mount technology placement machine cameras, which are used during the PCB assembly pick and place phase to identify and help place components in their respective locations. Typical positional tolerance of these cameras is +\/- 1 mil. Without fiducial markings to allow the SMT cameras to align properly, tombstone effect occurs because there is miss-registration between the pick-and-place camera and the board.\u00a0When it comes to fine pitch components, the PCB designer must make sure there are extra fiducials around those components to aid the SMT camera.<\/p>\n

Via-In Pad – <\/strong>Using via-in-pads for BGAs is another area the PCB layout designer must be careful about. Via-in-pad is widely popular, especially for finer pitch BGAs below 0.75 mm.\u00a0Compared with dog-bone fan-outs, via-in-pad increases density and allows the use of finer pitch packages.\u00a0Also, decoupling capacitors can be placed directly over the vias on the opposite side of the BGA, thus reducing intrinsic inductance.<\/p>\n

There are drawbacks as well as advantages to using via-in-pad.\u00a0When using via-in-pad, conductive and non-conductive material is used to fill the vias and then plated over.\u00a0If the fab house isn\u2019t knowledgeable about this process, a number of issues can occur. In particular, moisture entrapment is a risk, which wreaks havoc at assembly.\u00a0When moisture is trapped, vias and pads can be popped and dimples can form during reflow that can destroy BGA pads. A popular approach to avoiding extensive expansion or contraction is to use non-conductive via fillings, which reduces moisture entrapment.<\/p>\n

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Scenario #1: Reduce pad size to match trace width to avoid Tombstone effect<\/b>
\nTombstone is a component defect that occurs at the PCB assembly stage due to the solder\u2019s surface tension during re-flow.\u00a0As a result, one end of the component is detached from the board’s copper pad and lifts up vertically, resembling a tombstone.<\/p>\n

In this case, the PCB designer had reduced the pad size to match the trace width but unfortunately, it was reduced so much that this misstep violated IPC and manufacturing rules.<\/p>\n

The consequence was a number of issues in manufacturing and in particular, “tombstone effect” as shown in Figure 1<\/b>.<\/p>\n

\"Tombstone<\/a>

Figure 1: Tombstone Affect<\/strong><\/p><\/div>\n

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The decision to make the trace width as the same size as the pad was indeed correct: in any high-speed signal, discontinuities in impedance are created when a signal\u2019s geometry changes, which in turn changes impedance of a trace. By using the same trace width as the pad size, signal geometry would not change and the amount of discontinuity is reduced when the trace enters the leads of the discrete component pad.\u00a0In theory this works.\u00a0However, in practice, manufacturing issues arise when the same size is used for both traces and pads that are too small, resulting in tombstoning and other assembly issues.<\/p>\n

This situation came about when solder was flowing into the trace and it was the same size as the pad, and there was movement during reflow. The result was a mismatched pad size.\u00a0Together with other DFM issues, yields were below 60 percent, far below the expected 90 percent.<\/p>\n

Other DFM problems included:<\/p>\n