DFM Design for manufacturing
Helpful tips for applying DFM design for manufacturing. When designing High-speed PCB, lack of communication or assumptions between PCB designers and board manufacturers can lead to costly failures. Following are some real-world scenarios in which communication problems have occurred and some tips on how to avoid such problems.
Stepping through key layout stages –
About 75-80 percent of PCB layout errors occur due to incorrect part geometry or creation, bad hole definition, inadequate spacing between through holes and surface mount components, and lack of rework ability around critical components.
BGA – As a result the PCB design engineers have to move gingerly through various stages to avoid such fabrication and assembly problems. For example, (BGA) Ball Grid Array’s requiring rework may be placed too close together. As a result, rework cannot be performed. Also, vias or pads may be too close to the board’s edge, which can cause vias to be cut away during routing. Increased spacing is necessary for BGA efficiency. There are other issues arising from BGA use such as coefficient of thermal expansion (CTE) mismatches between the BGA and the boards due to improperly selected PCB material. If CTE is not comparable, solder joint fatigue can cause opens on the BGA. Also, symmetrical board stack-up is crucial when using BGAs. Otherwise, solder joint fatigue and board warping occur.
Fiducial Marks – There are fiducials, which are marks on a PCB that provide common measurable points for each and every assembly step. They permit PCB assembly systems to precisely zero in on the circuit pattern. Fiducials are used to properly align (SMT) surface mount technology placement machine cameras, which are used during the PCB assembly pick and place phase to identify and help place components in their respective locations. Typical positional tolerance of these cameras is +/- 1 mil. Without fiducial markings to allow the SMT cameras to align properly, tombstone effect occurs because there is miss-registration between the pick-and-place camera and the board. When it comes to fine pitch components, the PCB designer must make sure there are extra fiducials around those components to aid the SMT camera.
Via-In Pad – Using via-in-pads for BGAs is another area the PCB layout designer must be careful about. Via-in-pad is widely popular, especially for finer pitch BGAs below 0.75 mm. Compared with dog-bone fan-outs, via-in-pad increases density and allows the use of finer pitch packages. Also, decoupling capacitors can be placed directly over the vias on the opposite side of the BGA, thus reducing intrinsic inductance.
There are drawbacks as well as advantages to using via-in-pad. When using via-in-pad, conductive and non-conductive material is used to fill the vias and then plated over. If the fab house isn’t knowledgeable about this process, a number of issues can occur. In particular, moisture entrapment is a risk, which wreaks havoc at assembly. When moisture is trapped, vias and pads can be popped and dimples can form during reflow that can destroy BGA pads. A popular approach to avoiding extensive expansion or contraction is to use non-conductive via fillings, which reduces moisture entrapment.
Scenario #1: Reduce pad size to match trace width to avoid Tombstone effect
Tombstone is a component defect that occurs at the PCB assembly stage due to the solder’s surface tension during re-flow. As a result, one end of the component is detached from the board’s copper pad and lifts up vertically, resembling a tombstone.
In this case, the PCB designer had reduced the pad size to match the trace width but unfortunately, it was reduced so much that this misstep violated IPC and manufacturing rules.
The consequence was a number of issues in manufacturing and in particular, “tombstone effect” as shown in Figure 1.
The decision to make the trace width as the same size as the pad was indeed correct: in any high-speed signal, discontinuities in impedance are created when a signal’s geometry changes, which in turn changes impedance of a trace. By using the same trace width as the pad size, signal geometry would not change and the amount of discontinuity is reduced when the trace enters the leads of the discrete component pad. In theory this works. However, in practice, manufacturing issues arise when the same size is used for both traces and pads that are too small, resulting in tombstoning and other assembly issues.
This situation came about when solder was flowing into the trace and it was the same size as the pad, and there was movement during reflow. The result was a mismatched pad size. Together with other DFM issues, yields were below 60 percent, far below the expected 90 percent.
Other DFM problems included:
- Solder shorts caused by a gang relief mask
- Use of thermal vias caused solder wicking through the barrel
- Insufficient solder mask between two pads
Specifically, in this case, the fan out trace is the same size as a pad. Here a ball-grid array (BGA) package is used, with the BGA pads fanned out with a thicker trace. If it’s not a non-solder mask defined (NSMD) pad, the solder flows into the traces for those particular pads, causing a non-uniform pad size forming under the BGA, and subsequently forming cold solder joints or voids, as shown in Figure 2.
Scenario #2: RF filter problems
In this case, the high-speed design included a specialized RF filter in a three-pin SOP package. Solder mask was not used in between the pins and it was gang relieved, which is a method of defining a solder mask so that the mask is avoided around a group of pins. The result is a set of pins that don’t have solder mask in between. This may be done intentionally or may be a mistake on the part of the PCB designer. The result was solder shorts between the three pads of the filter.
Also, in this case the vias are extremely close to the pads. In fact, half the via encompasses the pad. That only happens if the via pad is on top of the component, rather than on the hole. This is not recommended: the hole should never overlap the component’s pad.
In this case, the via pads encroached on the component pad, which caused solder to wick through the barrel to cause tombstone effect and opens. There are a couple of ways to fan out of the discrete component to avoid this situation. With an eye to design for manufacturing, the best way is to position the via slightly further away from the pad where there is solder mask between the pad and the via hole.
A second way isn’t ideal for fan out. Here the via pad encroaches on the component pad, but not the hole. The result? When the via is tented, there is less likelihood of solder wicking through the barrel. There are two ways to solve this problem. The first option is to put the via directly on top of the pad and have it filled with a non-conductive fill. The second option is to move the via slightly and place solder mask between the hole and the pad.
For this particular high-speed design, a recommended land pattern from the manufacturer was used. The problem is that those recommendations were for low volume prototyping, not for production. A land pattern is one created in the CAD layout tool so that a PCB component can be soldered and makes connections to the PCB by means of an outline of the components as well as pads that will allow pins to be soldered to them.
But when a large number of parts is used on extremely dense boards, it is critically important that the land pattern be modified based on the assembly house’s recommendation.
Then there is the issue of the hole size. It has to be 0.3mm or less, so that the via closes very early in reflow. Ideally, it’s best to have the via shut and plated, but that never happens. For thermal vias, 0.3mm pitch or even finer is all that is necessary to prevent solder from wicking through the barrel.
In our high-speed design example, vias the OEM used measured about 15 mils, but ideally they should be less than 8 mils. Because they were not the correct size, during manufacturing solder was flowing down the barrel due to the larger vias. This caused a suction action on a separate SOP package in the board design that shorted out the peripheral pads (Figure 3).
Insufficient solder mask between two pads was a third DFM issue with this high-speed design. Here, pads were placed extremely close together. The result was that the solder mask was too thin, and it peeled off during the entire process. In turn, that caused solder to flow in a sliver from one pad to another. What had happened was that the discrete components didn’t have a uniform pad definition due to that lost sliver, as shown in Figure 4. Consequently, the component was being shifted from the smaller to the larger pad.
Another pad problem in this design had to do with mismatched pad sizes, this time in the power supply portion of the layout. Very fine 0402 metric (0.4 mm x 0.2 mm) passive device packages were used, which are not recommended for power layouts. In this situation a Savvy PCB layout engineer would have used 0603 thick film chip resistors with 1608 metric package sizes or maybe 0805 thick film chip resistors with slightly larger 2012 package sizes. But nothing smaller.
The reason for this caution is that most power layouts have large copper pours on external layers. In this high-speed design example with the 0402 packages, one side connecting directly to a copper blob. The other side just had a trace and a via. As a result during reflow, that copper blob acted as a heat sink producing a cold solder joint on one side of the pad. To alleviate that issue it is best to create thermal connections from the pad to the copper. Better yet, use a larger package.
Other examples of sabotaged DFM
There are other layout missteps that can sabotage efforts to apply effective DFM principles to printed circuit boards. Poorly executed PCB layout can cause fabrication and assembly problems relating to pad definition, component footprint, layer stack-up, material selection, fan out, trace width, and trace clearance. For example, poor pad definition can cause opens and shorts at assembly while an inaccurate component footprint can cause non-manufacturability if the component library isn’t correct.
At layer stack up, the designer has to make sure the right uniform stack-up is used to avoid warping. He or she also needs to know PCB material requirements to include field requirements. Meanwhile, a keen design eye has to be placed on fan out. If not performed properly, acid or etch traps occur, thus causing trace damage. Also, if not designed correctly, trace widths and clearances are other stages that can lead to shorts.
Fabrication stage problems. At this stage of the PCB design and fabrication process Warping occurs when small amounts of chemical, usually acidic, collect in what are called “acid traps” at the acute angles in a PCB trace. (Figure 5). When that chemical isn’t cleaned up, it can eat away at the traces even after assembly and/or it can cause intermittent connections while the product is in the field. Even in small amounts this can even eat away an entire trace if it is small enough and happens early at the trace width stage or later at the fan out stage of a layout.
Registration and aspect ratio issues When the PCB has many layers with fine lines and spacing they may cause mis-registration of holes and pads. Such registration problems on pads and vias during fabrication can cause multiple shorts, or even totally destroy the board.
Aspect ratio issues occur at early fabrication stages when the PCB goes into computer-aided manufacturing (CAM) and the fab shop finds out the aspect ratio isn’t correct. In this instance, hole sizes are extremely small and PCB thickness is considerable. Therefore, the fab shop either has major difficulties or isn’t able to fabricate that board.
Copper and solder mask slivers As discussed earlier, copper slivers come about because the PCB has copper features on external layers. Extremely small, one-ended copper traces – slivers – can protrude out of the PCB anywhere and any time to cause shorts after assembly.
Solder mask slivers occur when there isn’t enough solder mask between pads and vias. There are a number of causes for this phenomenon, including incorrect placement, incorrect pad definitions, and/or placing exposed vias too close to component pads.
These are some suggestion to avoid frustration and save money during prototype phase of PCB Design.
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